The present embodiments relate to transistor circuits, and are more particularly directed to differential silicon-on-insulator ("SOI") amplifiers having tied floating body connections.
The technology of many modern circuit applications continues to advance at a rapid pace, with one incredibly prolific type of circuit, and one which is highly developed, being digital memory. For such memories, consideration is given to all aspects of design, including maximizing efficiency and increasing performance. These considerations may be further evaluated based on the integrated circuit device in which the memory is formed, where such circuits may be implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. One often critical factor with respect to digital memories is the cost of the device. This cost is typically reflected in the overall size of the memory architecture. Another factor with respect to digital memories often includes the performance factor of overall circuit speed. Thus, a desirable memory reduces device size while providing acceptable functionality and speed.
In the current art, memory size may be affected by various factors. In one prior art approach, as detailed later, this size is affected by a connection used in each of the sense amplifiers of the memory configuration. Specifically, it is known in the memory art to include sense amplifier transistor configurations for either a dynamic random access memory (DRAM) or a static random access memory (SRAM). In either case, each sense amplifier transistor configuration includes two cross-coupled transistors connected to sense a differential voltage from one of the columns of the memory array. More particularly, the cross-coupled transistors amplify a small voltage difference, which represents the binary value being sensed, to a full scale signal. In the case of an SRAM, the differential voltage is measured between two bitlines. In the case of a DRAM, the differential voltage is measured between a bitline and a reference bitline. In either case, however, the cross-coupled transistor configuration which senses the differential voltage remains the same. Moreover, under current memory architectures, these cross-coupled transistors are sometimes formed using silicon-on-insulator (SOI) technology. In this instance, it is common to tie the body of each of the cross-coupled transistors to the source of the corresponding transistor. This is commonly done so that the body of each transistor is fixed to a known potential, rather than permitting the body potential to fluctuate which could otherwise occur due to the tendency of the body potential to deviate due to the signal conditions experienced by the transistor. While these source-to-body connections therefore provide acceptable operational performance, they also provide a drawback in that they require an additional connection per transistor and, thus, consume additional area on the integrated circuit in which the memory configuration is formed.
The above considerations and drawbacks are presented in more detailed fashion below. Additionally, however, note at the outset while the above is set forth in the context of digital memories, various of the same or similar considerations arise in other integrated circuits as well. Thus, in any of these contexts, there is a need to address these drawbacks, as is accomplished by the preferred embodiments which thus provide a more efficient and desirable integrated circuit configuration.